Abstract: To achieve the accuracy and stability of high-speed data transmission in large quantities, this paper designs a USB3.0 communication IP core interface suitable for FPGA development. Cypress’ s CYUSB3014 chip is used as USB3.0 device. The design of USB3.0 communication IP core interface is carried out by vivado software. the IP core is tested on USB3.0 high-speed data transmission system based on FPGA. The test results show that the IP core can actually achieve a maximum communication rate of 253.1 MB/s upstream and 131.9 MB/s downstream.