Abstract: A continuous time ultra-high speed broadband Σ-Δ analog-to-digital converter（ADC） with a clock sampling rate of 10 GS/s was presented based on 0.7 μm InP HBT process. The ADC system included a two-stage loop filter, a 2-bit analog to digital converter（ADC） and a 2-bit digital to analog converter（DAC）. In order to facilitate the test, a 2 bit DAC and an output buffer were added to the circuit. Circuit layout size of Σ-ΔADC was 1.58 mm×1.82 mm. The post simulation results show that when the sampling rate is 10 GS/s, for input signal frequency of 307 MHz, the ADC circuit has a spurious free dynamic range（SFDR） of 52.4 dB and a signal-to-noise ratio（SNR） of 42.6 dB. The ADC consumes 1.3 W under a supply voltage of 5 V.